Referring to FIG. 20, a first example of a conventional oscillator consisting of a semiconductor integrated circuit and a piezoelectric resonator for generating a clock signal to a computer or the like will be described below. A plurality of quartz oscillators 203 each including a piezoelectric resonator such as a quartz resonator 202 are mounted on a circuit board 201 of a computer system. Clock signals with various frequencies are generated by the respective quartz oscillators 203 and supplied to various units such as a CPU unit 204, an HDD unit 205, and communication units 206. Thus, the computer system needs as many quartz oscillators 203 as the number of clock frequencies. Furthermore, some units such as the CPU and HDD need a clock signal at a high frequency equal to or higher than 40 MHz. For such purpose, in the conventional technique, a clock signal is generated using a quartz oscillator operated in an overtone oscillation mode. FIG. 21 illustrates an example of a basic circuit of an overtone oscillator.
FIG. 22 illustrates a second example of a conventional PLL oscillator using a PLL circuit. This PLL oscillator includes an oscillation circuit coupled to a 14.31818-MHz quartz resonator for generating an oscillation signal and a PLL circuit which operates using the above oscillation signal as a reference signal. The frequency of the output signal is determined by the oscillation frequency of the quartz resonator and the frequency dividing ratio of a programmable frequency divider in the PLL circuit. The frequency dividing ratio of the programmable PLL frequency divider can be selected from two or more values so as to set the output frequency to a desired value.
Conventionally, a clock generator is realized using a quartz oscillator formed by combining a quartz resonator and an IC chip such as a CMOS IC chip. To generate a clock signal at a particularly high frequency supplied to a CPU, HDD, or the like, a quartz oscillator is operated in an overtone oscillation mode. However, the overtone oscillator circuit is difficult to operate in a stable fashion. More specifically, in the case of a 3rd-order overtone oscillator circuit, it is required that the circuit can selectively capture only a 3rd-order overtone signal while other signals at 1st- and 5th-order overtone frequencies should be suppressed. FIG. 23 illustrates a typical example of the negative resistance versus frequency characteristic of the overtone oscillator circuit. In FIG. 23, the curve 210 represents the characteristic of an oscillating circuit designed to operate at 50 MHz in the 3rd-order overtone mode. The negative resistance becomes maximum at 50 MHz corresponding to the 3rd-order overtone frequency, while the circuit has smaller negative resistances at 16.6 MHz corresponding to the 1st-order frequency and at 83.3 MHz corresponding to the 5th-order overtone frequency. As a result, oscillation occurs at 50 MHz corresponding to the 3rd-order overtone frequency. The negative resistance versus frequency characteristic varies depending on the gate capacitance (Cg), drain capacitance (Cd), feedback resistance (Rf), and the amplification factor (a) of an inverter. Therefore, if these parameters vary, the 3rd-order overtone oscillation can become unstable. As a result, even a jump to another order overtone mode can occur. More specifically, if the gate capacitance, drain capacitance, or feedback resistance increases, or the amplification factor of the inverter decreases, the negative resistance versus frequency characteristic shifts to left along the frequency axis This can cause a jump in oscillation to the fundamental frequency mode. On the other hand, if the gate capacitance, drain capacitance, or feedback resistance decreases, or the amplification factor of the inverter increases, the negative resistance versus frequency characteristic shifts to the right along the frequency axis, which can cause the oscillator to jump into the 5th-order overtone mode. Furthermore, the characteristics of each element of the oscillator have dependence on temperature and voltage. Therefore, the variations in temperature and/or voltage cause a change in the negative resistance versus frequency characteristic. In general, the negative resistance versus frequency characteristic shifts to the right along the frequency axis when the temperature is low and/or voltage is high, while the characteristic shifts to the left when the temperature is high and/or the voltage is low. This means that the overtone oscillator cannot be used in such environments in which large variations occur in the temperate and/or voltage. Furthermore, if the gate capacitance and/or drain capacitance are changed to adjust the oscillation frequency, a similar shift in the negative resistance versus frequency characteristic occurs, which can cause the 3rd-order overtone oscillation to become unstable and jump into another order overtone mode. Another disadvantage of the overtone oscillation is that the variable range of frequency is narrow compared to that of the fundamental frequency oscillation. Therefore, the overtone oscillation technique cannot be used in such applications in which a large variable frequency range is required.
In the second example of the PLL oscillator using a PLL circuit according to the conventional technique, the frequency is determined by the oscillation frequency of the quartz resonator, that is 14.31818 MHz in this specific example, and also by the frequency dividing ratio of a programmable frequency divider in the PLL circuit. The frequency dividing ratio of the programmable frequency divider is limited to integers, and thus there can be a difference between the actual frequency and a desired frequency. Therefore, if the application needs a high frequency accuracy, the PLL oscillator of this type cannot be employed. Another problem is that although the output frequency can be selected from 4 to 16 different preset values, other output frequencies are not available unless the frequency dividing ratio of the programmable frequency divider is redesigned. However, the implementation of the redesign requires a change in the aluminum pattern of the IC, which needs a long time and high cost.
Thus the general object of the present invention is to solve the above problems in the conventional techniques. It is a more specific object of the present invention to provide a PLL oscillator capable of generating a clock signal for use by a computer or the like at as high a frequency as 40 MHz or higher which cannot be easily generated by a quartz oscillator in a fundamental frequency mode, capable of operating in a stable fashion as the quartz oscillator in the fundamental frequency mode, capable of easily setting the output frequency to a desired value, capable of supplying it to a customer in a short delivery time (that is, capable of shipping it to a customer in a short time after receiving an order from the customer), capable of producing it at a low cost, capable of easily using it as the conventional quartz oscillator, and having a small size.